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MTV212MS64I View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV212MS64I Datasheet PDF : 26 Pages
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MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
TXABUF/TXBBUF emptying and generates a TXAI/TXBI (transmits buffer empty interrupt). S/W should write
the TXABUF/TXBBUF a new byte for the next transfer before shift register empties. A failure of this process
will cause data corrupt. The TXAI/TXBI occurs every time when shift register reads out the data from
TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.4 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. Since the EDID/VDIF data
and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212M64i only. In DDC2
mode and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL
condition by reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the
HSCL's rising edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0,
MTV212M64i will hold HSCL low to isolate the access to EEPROM of the host. A summary of master IIC
access is illustrated as follows.
7.4.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M64i transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.4.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M64i transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV212M64i receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please see the attachments about "Master IIC Receive Timing".
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SL VB ADR
DBUF
addr
00h (r/w)
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w)
08h (r)
08h (w)
09h (w)
0Ah (w)
bit7
DDC2
WadrB
MAckIn
TXBI
ETXBI
ENSlvA
ENSlvB
bit6
WadrA
Hifreq
RCBI
ERCBI
bit5
bit4
bit3
bit2
bit1
bit0
MAckO P
S
SlvRWB SAckIn SLVS
SlvAlsb1 SlvAlsb0
Hbusy
SlvBMI TXAI RCAI SlvAMI DbufI MbufI
SlvBMI
SlvAMI
MbufI
ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
DDC1 transmit data buffer
Revision 0.9
- 16 -
2000/11/17
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