VPLchg = 1
HFchg = 1
VFchg = 1
Vsync = 1
→ Indicates a VSYNC polarity change.
→ Indicates a HSYNC frequency change or counter overflow.
→ Indicates a VSYNC frequency change or counter overflow.
→ Indicates a VSYNC interrupt.
INTEN (w) : Interrupt enable.
EHPR = 1 → Enables HSYNC presence change interrupt.
EVPR = 1 → Enables VSYNC presence change interrupt.
EHPL = 1 → Enables HSYNC polarity change interrupt.
EVPL = 1 → Enables VSYNC polarity change interrupt.
EHF = 1 → Enables HSYNC frequency change / counter overflow interrupt.
EVF = 1 → Enables VSYNC frequency change / counter overflow interrupt.
EVsync = 1 → Enables VSYNC interrupt.
7. DDC & IIC Interface
7.1 DDC1 Mode
The MTV212M64i enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL
pin should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212M64i.
The shift register fetches data byte from the DDC1 data buffer (DBUF) then sends it in 9 bits packet formats
which includes a null bit (=1) as packet separator. The DBUF sets the DbufI interrupt flag when the shift
register reads out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the
DbufI is set. The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The
DbufI interrupt can be masked or enabled by EDbufI control bit.
7.2 DDC2B Mode
The MTV212M64i switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212M64i enters DDC2B mode, S/W can set IICpass control bit to allow HOST accessing EEPROM
directly. Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other
way to perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM
behavior. The slave address of Slave A block can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example,
if S/W chooses 5-bits slave address as 10100b, the slave IIC block A will respond to slave address
10100xxb and save the 2 LSB "xx" in XFR. This feature enables MTV212M64i to meet PC99 requirement.
The MTV212M64i will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it
will lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The
DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses to which MTV212M64i can respond. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The Slave A address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address matching the condition, then issues a
SlvAMI/SlvBMI interrupt. If the matched address is Slave A, MTV212M64i will save 2 LSB bits of the
matched address to SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then
written to RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address
(slave address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time
when the RCABUF/RCBBUF is loaded. If S/W is not able to read out the RCABUF/RCBBUF in time, the next
byte in shift register will not be written to RCABUF/RCBBUF and the slave block returns NACK to the master.
This feature guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W whether
the data in RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address matching the condition, then issues a
SlvAMI/SlvBMI interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is
Slave A, and the data pre-stored in the TXABUF/TXBBUF is loaded into shift register, resulting in
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