MTV112AN View Datasheet(PDF) - Myson Century Inc

Part Name

Description

Manufacturer

MTV112AN

8051 Embedded CRT Monitor Controller MASK Version

Myson Century Inc 

MYSON

TECHNOLOGY

MTV112A

(Rev 1.9)

P51E = 1 → Pin #38 is P5.1.

= 0 → Pin #38 is DA1.

P50E = 1 → Pin #39 is P5.0.

= 0 → Pin #39 is DA0.

MORE = 1 → Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,

EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is

controlled by (MCLK1,MCLK0) bits.

= 0 → above bits internal keep “0” by MTV112A, and master IIC speed is controlled by

IICF bit.

* SINT0 should be 0 in this case.

2. Memory Allocation

2.1 Internal Special Function Registers (SFR)

SFR is a group of registers that is the same as standard 8051.

2.2 Internal RAM

There is a 384 bytes RAM in MTV112A. The first portion of the RAM area contains 256 bytes, accessible by

setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.

2.3 External Special Function Registers (XFR)

XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for

monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access

these registers.

FFH Accessible by indirect

addressing only.

The value of PSW.1 =

both 0 and 1.

(Using MOV A, @Ri

80H

instruction)

7FH

Accessible by direct

and indirect

addressing.

PSW.1=0

00H

SFR

Accessible by direct

addressing.

Accessible by direct

and indirect

addressing.

PSW.1 =1

FFH

XFR

Accessible by indirect

external RAM

addressing.

(Using MOVX A, @Ri

00H

Instruction.)

3. PWM DAC

Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk

is X’tal or 2 * X’tal, selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253

or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register

generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's

content is FFH. Writing 00H to the DAC register generates stable low output.

reg name

DA0

DA1

DA2

DA3

addr

20h (r/w)

21h (r/w)

22h (r/w)

23h (r/w)

bit7

DA0b7

DA1b7

DA2b7

DA3b7

bit6

DA0b6

DA1b6

DA2b6

DA3b6

bit5

DA0b5

DA1b5

DA2b5

DA3b5

bit4

DA0b4

DA1b4

DA2b4

DA3b4

bit3

DA0b3

DA1b3

DA2b3

DA3b3

bit2 bit1 bit0

DA0b2 DA0b1 DA0b0

DA1b2 DA1b1 DA1b0

DA2b2 DA2b1 DA2b0

DA3b2 DA3b1 DA3b0

MTV112A Revision 1.9 05/18/2001

5/20

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