FIN1108MTD View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
FIN1108MTD Datasheet PDF : 7 Pages
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AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
tPLHD
Differential Output Propagation Delay
LOW-to-HIGH
0.75
1.1
1.75
ns
tPHLD
tTLHD
tTHLD
tSK(P)
tSK(LH),
tSK(HL)
tSK(PP)
fMAX
tPZHD
Differential Output Propagation Delay
HIGH-to-LOW
RL = 100 Ω, CL = 5 pF,
Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV,
Differential Output Fall Time (80% to 20%) VIC = VID/2 to VCC − (VID/2),
Pulse Skew |tPLH - tPHL|
Duty Cycle = 50%,
Channel-to-Channel Skew
See Figure 1 and Figure 1
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
0.75
1.1
1.75
ns
0.29
0.4
0.58
ns
0.29
0.4
0.58
ns
0.02
0.2
ns
0.02
0.15
ns
0.02
0.5
ns
400
>630
MHz
3
5
ns
tPZLD
tPHZD
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
RL = 100 Ω, CL = 5 pF,
See Figure 2 and Figure 3
3.1
5
ns
2.2
5
ns
tPLZD
Differential Output Disable Time
from LOW to Z
tDJ
LVDS Data Jitter,
VID = 300 mV, PRBS = 223 - 1,
Deterministic
VIC = 1.2V at 800 Mbps
tRJ
LVDS Clock Jitter,
VID = 300 mV,
Random (RMS)
VIC = 1.2V at 400 MHz
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
2.5
5
ns
80
135
ps
1.9
3.5
ps
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output VOD > 250 mV and the duty cycle is better than 45% / 55% with all channels switching.
Note 7: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency = 10 MHz, tR
or tF < = 0.5 ns
Note B: CL includes all probe and jig capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
5
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