33937A_11 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

33937A_11

Three Phase Field Effect Transistor Pre-driver

Freescale Semiconductor 

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

VLS UNDER VOLTAGE

Since VLS supplies both the gate driver circuits and the

gate voltage, it is critical that it maintains sufficient potential

to place the power stage FETs in saturation. Since proper

operation cannot continue with insufficient levels, a low VLS

condition will shutdown driver operation. The VLS Under

Voltage threshold is between 7.5 V and 8.5 V. When a

decreasing level reaches the threshold, both the HS and the

LS output gate circuit drive the gates OFF for about 8us

before reducing the drive to hold off levels. Since low VLS is

a condition for turning on the Hold Off circuit, Hold Off then

provides a weak pull-down on all gates. A filter timeout of

about 700ns insures that noise on VLS will not cause

premature protective action.

When VLS rises above this threshold again, the LS Gate

immediately follows the level of the input. However, a short

initialization sequence must be executed to restore operation

of the HS Gate. (See Initialization Requirements on page 37)

Since VLS is no longer under voltage, the Hold Off circuit is

turned off and the HS Gate will be in a high-impedance state

until the LS Gate responds to an input command to turn off.

HOLD OFF CIRCUIT

The IC guarantees the output FETs are turned off in the

absence of VDD or VPWR by means of the Hold off circuit. A

small current source, generated from VSUP, typically

100 µA, is mirrored and pulls all the output gate drive pins low

when VDD is less than about 3.0 V, RST is active (low), or

when VLS is lower than the VLS_Disable threshold. A

minimum of 3.0 V is required on VSUP to energize the Hold

off circuit.

CHARGE PUMP

The Charge Pump circuit provides the basic switching

elements required to implement a charge pump, when

combined with external capacitors and diodes for enhanced

low-voltage operation.

When the 33937A is connected per the typical application

using the charge pump (see Figure 22), the regulation path

for VLS includes the charge pump and a linear regulator. The

regulation set point for the linear regulator is nominally at

15.34 V. As long as VLS output voltage (VLSOUT) is greater

than the VLS analog regulator threshold (VLSATH) minus

VTHREG, the charge pump is not active.

If VLSOUT < VLSATH – VTHREG the charge pump turns ON

until VLSOUT > VLSATH – VTHREG + VHYST

VHYST is approximately 200 mV. VLSATH will not interfere

with this cycle even when there is overlap in the thresholds,

due to the design of the regulator system.

The maximum current the charge pump can supply is

dependent on the pump capacitor value and quality, the

pump frequency (nominally 130 kHz), and the Rdson of the

pump FETs. The effective charge voltage for the pump

capacitor would be VSYS – 2 * VDIODE. The total charge

transfer would then be CPUMP * (VSYS – 2*VDIODE).

Multiplying by the switch frequency gives the theoretical

current the pump can transfer: FPUMP * CPUMP * (VSYS –

2*VDIODE).

NOTE: There is also another smaller, fully integrated

charge pump (Trickle Charge Pump - see Figure 2), which is

used to maintain the High Side drivers’ gate VGS in 100

percent duty cycle modes.

33937A

28

Analog Integrated Circuit Device Data

Freescale Semiconductor

Share Link: