MAX132 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX132 Datasheet PDF : 16 Pages
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±18-Bit ADC with Serial Interface
____________Functional Description
The MAX132 integrates the input voltage for a fixed
period of time, then deintegrates a known reference
voltage and measures the time required to reach zero.
Good line rejection is achieved by setting the (input)
integration time equal to one 50Hz or 60Hz period. The
MAX132 has a 50Hz/60Hz mode selection bit that sets
the integration time to 655/545 clock periods, respec-
tively, so that 50Hz/60Hz rejection is obtained with a
32,768Hz crystal. The MAX132 is tested and guaran-
teed at a 16 conv/sec throughput rate. Figure 1 shows
the basic MAX132 application circuit, with component
values selected for 16 conv/sec .
For applications that don’t require 50Hz/60Hz rejection,
the MAX132 will operate up to 100 conv/sec at reduced
accuracy (typically 0.012% FSR nonlinearity, or ±13
bits). In these applications, the 50Hz mode is recom-
mended because of its longer (655 count) integration
time. See Increased Speed section.
__________Analog Design Procedure
Input Voltage Range
and Input Protection
The recommended analog full-scale input range is
±512mV. Performance is tested and guaranteed at
±512mV full scale, corresponding to a 2µV/LSB resolu-
tion at 18 bits. Resolution is defined as follows:
[ ] Resolution Volts / LSB = VIN(FS) / 262,144
which corresponds to 2µV/LSB resolution at 18 bits.
Consult the Typical Operating Characteristics for Noise
vs. Number of Samples Averaged and other important
operating parameters. Note how accuracy depends on
common-mode input voltage (common mode is defined
here as |VIN LO - AGND|). For optimum performance,
set the analog input full-scale between ±470mV and
CS
SCLK
DIN
DOUT
t1
t6
t3
t7
MSB IN
t8
MSB OUT
t4
B6–B1
B6–B1
t5
t2
LSB IN
t9
t10
LSB OUT
P0–P3
Figure 2. Serial-Mode Timing
+5V
t11, t12
+5V
3k
DOUT
DOUT
3k
CL
CL
DGND
DGND
a. High-Z to VOH (t8)
b. High-Z to VOL (t8)
Figure 3. Load Circuits for Access Time
3k
DOUT
3k
DOUT
10pF
10pF
DGND
DGND
a. VOH to High-Z (t10)
b. VOL to High-Z (t10)
Figure 4. Load Circuits for Disable Time to Three-State
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