S-1122 View Datasheet(PDF) - Unspecified
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S-1122 Datasheet PDF : 31 Pages
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HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.6.1_02
S-1112/1122 Series
3. ON/OFF pin
This pin starts and stops the regulator.
When the ON/OFF pin is set to OFF level, the entire internal circuit stops operating, and the built-in
P-channel MOS FET output transistor between the VIN pin and the VOUT pin is turned off, reducing
current consumption significantly. The VOUT pin becomes the VSS level due to the internally divided
resistance of several M between the VOUT pin and the VSS pin.
The structure of the ON/OFF pin is as shown in Figure 13. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating status. In addition, note that the current consumption
increases if a voltage of 0.3 V to VIN – 0.3 V is applied to the ON/OFF pin. When not using the ON/OFF
pin, connect it to the VSS pin in the product A type, and connect it to the VIN pin in B type.
Table 8
Product Type
A
A
B
B
ON/OFF Pin
“L”: ON
“H”: OFF
“L”: OFF
“H”: ON
Internal Circuit
Operate
Stop
Stop
Operate
VOUT Pin Voltage
Set value
VSS level
VSS level
Set value
Current Consumption
ISS1
ISS2
ISS2
ISS1
VIN
ON/OFF
VSS
Figure 13
Selection of Output Capacitor (CL)
The S-1112/1122 Series requires an output capacitor between the VOUT pin and the VSS pin for phase
compensation. A ceramic capacitor with a capacitance of 0.47 F or more can be used. When using an OS
capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 0.47 F or
more, and the ESR must be 10 or less.
The value of the output overshoot or undershoot transient response varies depending on the value of the
output capacitor.
When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
15
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