A Microchip Technology Company
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
0.5 VDD
0.4 VDD
0.3 VDD
Thigh
0.6 VDD
Tcyc
Tlow
0.2 VDD
Figure 8: CLK Waveform
0.4 VDD p-to-p
(minimum)
1161 F11.0
AC Characteristics (FWH Mode)
Table 17:Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol Parameter
Min
Max
TCYC
TSU
TDH
TVAL1
TBP
TSE
TBE
TSCE
TON
TOFF
Clock Cycle Time
Data Set Up Time to Clock Rising
Clock Rising to Data Hold Time
Clock Rising to Data Valid
Byte Programming Time
Sector-Erase Time
Block-Erase Time
Chip-Erase Time
Clock Rising to Active (Float to Active Delay)
Clock Rising to Inactive (Active to Float Delay)
30
7
0
2
11
20
25
25
100
2
28
1. Minimum and maximum times have different loads. See PCI spec.
Units
ns
ns
ns
ns
µs
ms
ms
ms
ns
ns
T17.3 25085
©2011 Silicon Storage Technology, Inc.
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