FDMF8704 View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

FDMF8704

High Current / High Frequency FET plus Driver Multi-chip Module

Fairchild Semiconductor 

Functional Block Diagram

VCIN

DISB

PWM

HSEN

BOOT HDRV VIN

Q1

VCIN

VSWH

Q2

CGND

LDRV PGND

Figure 3. Functional Block Diagram

Functional Description

The FDMF8704 is a driver plus FET module optimized for

synchronous buck converter topology. A single PWM input

signal is all that is required to properly drive the high-side and

the low-side MOSFETs. Each part is capable of driving speeds

up to 1MHz.

Low-Side Driver

The low-side driver (LDRV) is designed to drive a ground

referenced low RDS(ON) N-channel MOSFET. The bias for LDRV

is internally connected between VCIN and CGND. When the

driver is enabled, the driver's output is 180° out of phase with

the PWM input. When the driver is disabled (DISB = 0V), LDRV

is held low.

High-Side Driver

The high-side driver (HDRV) is designed to drive a floating

N-channel MOSFET. The bias voltage for the high-side driver is

developed by a bootstrap supply circuit, consisting of the

external diode and external bootstrap capacitor (CBOOT). During

start-up, VSWH is held at PGND, allowing CBOOT to charge to

VCIN through the internal diode. When the PWM input goes

high, HDRV will begin to charge the high-side MOSFET's gate

(Q1). During this transition, charge is removed from CBOOT and

delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN,

forcing the BOOT pin to VIN +VC(BOOT), which provides

sufficient VGS enhancement for Q1. To complete the switching

cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then

recharged to VCIN when VSWH falls to PGND. HDRV output is

in phase with the PWM input. When the driver is disabled, the

high-side gate is held low.

Adaptive Gate Drive Circuit

The driver IC embodies an advanced design that ensures

minimum MOSFET dead-time while eliminating potential shoot-

through (cross-conduction) currents. It senses the state of the

MOSFETs and adjusts the gate drive, adaptively, to ensure they

do not conduct simultaneously. Refer to Figure 4 and 5 for the

relevant timing waveforms. To prevent overlap during the low-

to-high switching transition (Q2 OFF to Q1 ON), the adaptive

circuitry monitors the voltage at the LDRV pin. When the PWM

signal goes HIGH, Q2 will begin to turn OFF after some

propagation delay (tPDL(LDRV)). Once the LDRV pin is

discharged below ~1.2V, Q1 begins to turn ON after adaptive

delay tPDH(HDRV). To preclude overlap during the high-to-low

transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors

the voltage at the SW pin. When the PWM signal goes LOW, Q1

will begin to turn OFF after some propagation delay

(tPDL(HDRV)). Once the VSWH pin falls below ~2.2V, Q2 begins

to turn ON after adaptive delay tPDH(LDRV). Additionally, VGS of

Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a

secondary adaptive delay is initiated, which results in Q2 being

driven ON after tPDH(LDRV), regardless of SW state. This

function is implemented to ensure CBOOT is recharged each

switching cycle, particularly for cases where the power

converter is sinking current and SW voltage does not fall below

the 2.2V adaptive threshold. Secondary delay tPDH(HDRV) is

longer than tPDH(LDRV).

4

www.fairchildsemi.com

FDMF8704 Rev. F2

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