IDT7015S35JB(1996) View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7015S35JB
(Rev.:1996)

HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7015S/L

HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3)

tWH

Write Hold After BUSY(5)

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

IDT7015X12

Com'l. Only

Min. Max.

IDT7015X15

Com'l. Only

Min. Max

IDT7015X17

Com'l. Only

Min Max. Unit

—

12

—

12

—

12

—

12

5

—

—

15

11

—

—

15

—

15

—

15

—

15

5

—

— 18

13

—

—

17 ns

—

17 ns

—

17 ns

—

17 ns

5

— ns

—

18 ns

13

— ns

0

—

0

—

11

—

13

—

0

— ns

13

— ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

25

—

30

—

20

—

25

— 30 ns

— 25 ns

IDT7015X20 IDT7015X25 IDT7015X35

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3)

tWH

Write Hold After BUSY(5)

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

Min. Max. Min. Max. Min. Max. Unit

—

20

—

20

—

20 ns

—

20

—

20

—

20 ns

—

20

—

20

—

20 ns

—

17

—

17

—

20 ns

5

—

5

—

5

— ns

—

30

—

30

—

35 ns

15

—

17

—

25

— ns

0

—

0

—

0

— ns

15

—

17

—

25

— ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

45

—

50

—

60 ns

—

30

—

35

—

45 ns

NOTES:

2940 tbl 13

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

6.12

12

Share Link: