IDT70261L15PF(2000) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT70261L15PF
(Rev.:2000)
(Rev.:2000)
Integrated Device Technology
IDT70261L15PF Datasheet PDF : 19 Pages
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IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Truth Table IV
Address BUSY Arbitration
Inputs
Outputs
CEL CER
AOL-A13L
AOR-A13R
BUSYL(1) BUSYR(1)
Function
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
LL
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
3039 tbl 17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Le ft Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Rig ht Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Le ft Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Le ft Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Rig ht Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Le ft Port Writes "1" to Semaphore
1
1
Semaphore free
Rig ht Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Rig ht Port Writes "1" to Semaphore
1
1
Semaphore free
Le ft Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Le ft Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
3039 tbl 18
Functional Description
The IDT70261 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70261 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE = VIH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
III. The left port clears the interrupt through access of address location
3FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
port interrupt flag (INTR) is asserted when the left port writes to memory
location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port
must read the memory location 3FFF. The message (16 bits) at 3FFE or
3FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and 3FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
61.452
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