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M4-128/128-14YC View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
Manufacturer
M4-128/128-14YC
Lattice
Lattice Semiconductor Lattice
M4-128/128-14YC Datasheet PDF : 46 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
FUNCTIONAL DESCRIPTION
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL®
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In MACH 4 architecture, the macrocells are flexibly coupled to the product terms through the
logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch
matrix. In addition, more input routing options are provided by the input switch matrix. These
resources provide the flexibility needed to fit designs efficiently.
Clock/Input
Pins
Note 3
Dedicated
Input Pins
4
Clock
Generator
Note 2
PAL Block
33/
34/
I/O
36
Logic
Array
Logic 16 Output/ 16
Allocator
Buried
8
Pins
with XOR
Macrocells
Note 1
Input
Switch
Matrix
16
16
I/O
Pins
PAL Block
PAL Block
Figure 1. MACH 4 Block Diagram and PAL Block Structure
I/O
Pins
17466G-001
Notes:
1. 16 for MACH 4 devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4(LV)-32/32.
3. M4(LV)-192/96 and M4(LV)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central
switch matrix.
MACH 4 Family
5
 

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