5962-9960601TUX View Datasheet(PDF) - Aeroflex Corporation
Part Name
Description
Manufacturer
5962-9960601TUX Datasheet PDF : 16 Pages
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Standard Products
QCOTSTM UT7Q512 512K x 8 SRAM
Data Sheet
August, 2002
FEATURES
q 100ns (5 volt supply) maximum address access time
q Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
q TTL compatible inputs and output levels, three-state
bidirectional data bus
q Typical radiation performance
- Total dose: 30krad(Si)
- 30krad(Si) to 300krad(Si), depending on orbit, using
Aeroflex UTMC patented shielded package
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = 5MeV-cm 2/mg
- Saturated Cross Section (cm2) per bit, ~1.0E-7
- 1.5E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
q Packaging options:
- 32-lead ceramic flatpack (weight 2.5-2.6 grams)
q Standard Microcircuit Drawing 5962-99606
- QML T and Q compliant
INTRODUCTION
The QCOTSTM UT7Q512 Quantified Commercial Off-the-
Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable ( E),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking the Chip
Enable One ( E) input LOW and the Write Enable ( W) input
LOW. Data on the eight I/O pins (DQ0 through DQ7) is then
written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking Chip Enable One (E) and Output Enable (G) LOW
while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified
by the address pins will appear on the eight I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (E,
HIGH), the outputs are disabled (G HIGH), or during a write
operation (E LOW and W LOW).
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ 0 - DQ 7
Data
Control
CLK
Gen.
Memory Array
1024 Rows
512x8 Columns
I/O Circuit
Column Select
E
W
G
Figure 1. UT7Q512 SRAM Block Diagram
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