PS12012-A View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

PS12012-A

FLAT-BASE TYPE INSULATED TYPE

MITSUBISHI ELECTRIC  

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12012-A

FLAT-BASE TYPE

INSULATED TYPE

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

LINEARITY

5

VC–

4 min max

VC–(200%)

VDH=15V

VDL=5V

TC=–20~100˚C

3

VC0

2

VC+(200%)

1

Analogue output signal

data hold range

VC+

0

–400 –300 –200 –100 0 100 200 300 400

Real load current peak value.(%)(Ic=Io! 2)

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

“DATA HOLD” DEFINITION

VC

500µs

0V

VCH(5µs)

VCH(505µs)

rCH=

VCH(505µs)-VCH(5µs)

VCH(5µs)

Note ; Ringing happens around the point where the signal output

voltage changes state from “analogue” to “data hold” due

to test circuit arrangement and instrumentational trouble.

Therefore, the rate of change is measured at a 5 µs delayed point.

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

Input signal VCIN(p) of each phase upper arm 0V

Input signal VCIN(n) of each phase lower arm

0V

Gate signal Vo(p) of each phase upper arm

(ASIPM internal)

0V

Gate signal Vo(n) of each phase upper arm

(ASIPM internal)

0V

Error output FO1 0V

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in “LOW” level.

By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input

interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

whichever comes in later.

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Input signal VCIN of each phase

upper arm

0V

Short circuit sensing signal VS

0V

Gate signal Vo of each phase

upper arm(ASIPM internal)

0V

Error output FO1 0V

SC delay time

Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).

Jan. 2000

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