MTV012E View Datasheet(PDF) - Unspecified
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MTV012E Datasheet PDF : 14 Pages
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MYSON
TECHNOLOGY
MTV012E
5.2 DDC2B Mode
MTV012E switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV012E enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the
HSDA and HSCL are directly bypassed to ISDA and ISCL pins. MTV012E will return to DDC1 mode if
HSCL is kept high for a 128-VSYNC clock period. However, it will 100K in DDC2B mode if a valid IIC
access has been detected on the HSCL/HSDA bus. The DDC2 flag reflects the current DDC status; S/W
may clear it by setting CLRDDC. The control bits M128/M256 are used to block the EEPROM write
operation from the host if the address is over 128/256.
5.3 Master Mode IIC Function Block
The master mode IIC block is connected to the ISDA and ISCL pins. The software program can access
the external EEPROM through this interface. Since the EDID/VDIF data and the display information
share the common EEPROM, precaution must be taken to avoid bus conflict. In DDC1 mode, the IIC
interface is controlled by MTV012E only. In DDC2B mode, the host may access the EEPROM directly.
Software can test the HSCL condition by reading the BUSY flag, which is set in case of HSCL=0. A
summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM
1. Write to MBUF the EEPROM slave address (bit 0 = 0).
2. Set S bit to Start.
3. After MTV012E transmits this byte, a MI interrupt will be triggered.
4. The program can write MBUF to transfer the next byte, or set the P bit to stop.
* Please see the attachments about "Master IIC Transmission Timing".
5.3.2. To Read EEPROM
1. Write to MBUF the slave address (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV012E transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out to MBUF the useless byte in order to continue the data transfer.
6. After MTV012E receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but the P bit needs to be set before reading
can terminate the operation.
* Please see the attachments about the "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL pins or ISDA/ISCL pins, and selected by the
SLVsel control bit. This block is receiving mode only. S/W may set the SLVADR register to determine the
address range to which this block should respond. The block first detects an IIC slave address match
condition, then issues a SLVMI interrupt. The data received from SDA is shifted onto the shift register
and moved to the SLVBUF latch. The first byte loaded is the word address (the slave address is
dropped). This block also generates a SLVBI each time the SLVBUF is loaded. If S/W can't read out the
SLVBUF in time, the next byte will not be written to SLVBUF and the slave block returns NACK to the
master. This feature guarantees the data integrity of communication. A WADR flag can tell S/W if the
data in SLVBUF is a word address.
* Please see the attachments about "Slave IIC Block Timing".
6. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip
reset signal. After the power supply is above 4.0V, LVR maintains the reset state for a 144 Xtal cycle to
guarantee that the chip exit reset condition has a stable Xtal oscillation. The specific time of power
supply in the low level is 3us and is adjustable by an external capacitor connected to the RST pin.
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT(2:0). The
10/14
MTV012E Revision 1.2 12/23/1998
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