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MTV003 View Datasheet(PDF) - Unspecified

Part Name
Description
Manufacturer
MTV003 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MYSON
TECHNOLOGY
MTV003N
(MTV003)
V-Freq(Hz)
1 20
2 56.25
3 59.94
4 60
5 60.32
6 60.53
7 66.67
8 70.069
9 70.08
10 72
11 72.378
12 72.7
13 87
Output value hexadecimal 9 bits decimal
30D
781
115
277
104
260
104
260
103
259
102
258
0EA
234
0DE
222
0DE
222
0D9
217
0D7
215
0D6
214
0B3
179
Tolerance (%)
0.12804
0.36101
0.38461
0.38461
0.38610
0.38759
0.42735
0.45045
0.45045
0.46082
0.46511
0.46728
0.55865
3.6 Command Interface
The command interface contains 3 pins. Each transfer of command is comprised of 16 DCK clock periods. The
first 8 DCK clocks are for the address and direction of DIO, and the succeeding 8 DCK clocks are for the data.
Each transfer is initiated by setting CMDB Low. The CMDB pin must be pulled High after data transfer is
completed.
- Command Format
B0 - 4 (ADD4 - 0)
B5 (W/RB)
B6 - 7
B8 - 15 (DA0 - 7)
(DA7 - 0)
- Register Allocation
a. Read Transfer
: Address of the registers.
: Transfer direction, 1=write, 0=read.
: Reserved.
: Data input when W/RB=1.
Data output when W/RB=0.
Reg #
Reg0
Reg1
Reg2
Reg3
Reg4
Address Portion
ADD4-0 W/RB
B0 - 4
B5
B8
00000
0
Hpol
00001
0
x
00010
0
HF7
00011
0
x
00100
0
VF7
Data Portion
DA7 - 0
B9 B10 B11 B12 B13 B14 B15
Vpol HSpre VSpre HVpre Hsl
Vsl
x
x
x
x
HCFF HF10 HF9
HF8
HF6
HF5
HF4
HF3
HF2
HF1
HF0
x
x
x
x
x
VCFF VF8
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Table 4
b. Write Transfer
Reg #
Reg0
Reg1
Reg2
Reg3
Address Portion
ADD4-0 W/RB
B0 - 4
B5
00000
1
00001
1
00010
1
00011
1
B8
x
Vpf0
x
CLK4M
B9
x
Vpf1
x
TEST
B10
x
Hpf0
x
x
5/13
Data Portion
DA0 - 7
B11 B12
x
x
Hpf1
VBpl
x
x
x
x
B13
x
HBpl
x
x
B14
x
HVcvs
x
x
B15
x
x
x
x
MTV003 Revision 2.3 07/01/1998
 

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