QL6325E Eclipse-E Data Sheet Rev. F
Table 24: PQ208 Pin Descriptions (Continued)
Pin
INREF(A)
PLLOUT
IOCTRL(A)
VPUMP
VDED
VDED2
VCCPLL
PLL_RESET
Direction
Function
I Differential reference voltage
O PLL output pin
I Highdrive input
I Charge Pump Disable
I
Voltage tolerance for clocks,
TDO JTAG output, and IOCTRL
I
Voltage tolerance for JTAG pins
(TDI, TMS, TCK, and TRSTB)
I Power Supply pin for PLL
I PLL reset pin
Description
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
Table 12 for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if voltage referenced standards are not
used.
Dedicated PLL output pin. Must be left unconnected if the
PLL is not driven off chip. PLLOUT pin is driven by VCCIO.
For a list of each PLLOUT pin and the VCCIO pin that powers
it see Table 26.
This pin provides fast RESET, SET, CLOCK, and ENABLE
access to the I/O cell flip-flops, providing fast clock-to-out and
fast I/O response times. This pin can also double as a high-
drive pin to the internal logic cells. The A inside the
parenthesis means that IOCTRL is located in Bank A. There
is an internal pulldown resistor to GND on this pin. This pin
should be tied to GND if it is not used. For backwards
compatibility with Eclipse and EclipsePlus, it can be tied to
VDED or GND. If tied to VDED, it will draw no more than
20 µA per IOCTRL pin due to the pulldown resistor. The
voltage tolerance of this pin is specified by VDED.
This pin disables the internal charge pump for lower static
power consumption. To disable the charge pump, connect
VPUMP to 3.3 V. If the Disable Charge Pump feature is not
used, connect VPUMP to GND. For backwards compatibility
with Eclipse and EclipsePlus devices, connect VPUMP to
GND.
This pin specifies the input voltage tolerance for CLK,
DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well
as the output voltage drive TDO JTAG pins. If the PLLs are
used, VDED must be 2.5 V or 3.3 V. The legal range for
VDED is between 1.71 V and 3.6 V. For backwards
compatibility with Eclipse and EclipsePlus devices, connect
VDED to 2.5 V.
These pins specify the input voltage tolerance for the JTAG
input pins. The legal range for VDED2 is between 1.71 V and
3.6 V. These do not specify output voltage of the JTAG output,
TDO. Refer to the VDED pin section for specifying the JTAG
output voltage. VDED2 must be egual to or greater than
VDED.
Connect to 2.5 V supply. Even if your design does not utilize
the PLLs, you must connect VCCPLL to 2.5 V.
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted
and then released in order for the LOCK_DETECT to work.
If a PLL module is not used, then the associated PLLRST<x>
must be connected to VDED.
© 2005 QuickLogic Corporation
www.quicklogic.com
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