SST89C54 View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST89C54

FlashFlex51 MCU

Silicon Storage Technology 

IN-APPLICATION PROGRAMMING MODE

The SST89C54/58 offers 20/36 KByte of In-Application

Programmable flash memory. During In-Application Pro-

gramming, the CPU of the microcontroller enters IAP

Mode. The two blocks of flash memory allows the CPU

to concurrently execute user code from one block, while

the other is being reprogrammed. The CPU may also

fetch code from an external memory while all internal

flash is being reprogrammed. The chip can start the In-

Application Programming operation either with the exter-

nal program code execution being enabled (EA# = L) or

disabled (EA#=H). The mailbox registers (SFST, SFCM,

SFAL, SFAH, SFDT and SFCF) located in the Special

Function Register (SFR), control and monitor the

device’s erase and program process.

Table 6 outlines the commands and their associated

settings of the mailbox registers.

In-Application Programming Mode Clock Source

During IAP Mode, both the CPU core and the flash

controller unit are driven off the external clock. However,

an internal oscillator will provide timing references for

Program and Erase operations. The duration of Program

and Erase operations will be identical between External

Host Mode and In-Application Mode. The internal oscil-

lator is only turned on when required, and is turned off as

soon as the Flash operations complete.

IAP Enable Bit

The IAP Enable Bit, SFCF[6], initializes In-Application

Programming mode, enabling IAP command decoding.

Until this bit is set all flash programming IAP commands

will be ignored.

In-Application Programming Mode Commands

All of the following commands can only be initiated in the

IAP Mode. In all situations, writing the control byte to the

(SFCM) register will initiate all of the operations. All

commands (except CHIP-ERASE) will not be enabled if

the security features are enabled on the selected

memory block. The critical timing for all Erase and

Program commands, is self-generated by the on-chip

flash controller unit.

FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

The two Program commands are for programming new

data into the memory array. The portion of the memory

array to be programmed should be in the erased state,

FFh. If the memory is not erased, then erase it with an

appropriate Erase command. Warning: Do not write

(program or erase) to a block that the code is cur-

rently fetching from. This will cause unpredictable

program behavior and may corrupt program data.

The CHIP-ERASE command erases all bytes in both

memory blocks (16/32K and 4K). This command ignores

the Security Lock status and will erase the security lock

bits and Re-Map bits. The CHIP-ERASE command

sequence is as follows:

IAP Enable

ORL SFCF, #40h

Set-Up

MOV SFDT, #55h

Polling scheme

MOV SFCM, #01h

Interrupt scheme

MOV SFCM, #81h

SFST[2] indicates

operation completion

INT1# occurrence

indicates completion

344 ILL F39.2

The BLOCK-ERASE command erases all bytes in one of

the two memory blocks (16/32K or 4K). The selection of

the memory block to be erased is determined by the

“A15” bit (SFAH[7]) of the SuperFlash Address Register.

If SFAH[7] = 0b, the primary flash memory Block 0 is

selected (16/32K). If SFAH[7:4] = Fh, the secondary

flash memory Block 1 is selected (4K). The BLOCK-

ERASE command sequence is as follows:

© 2000 Silicon Storage Technology, Inc.

26

344-2 8/00

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