SST89C54 View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST89C54

FlashFlex51 MCU

Silicon Storage Technology 

FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

The BYTE-PROGRAM and BURST-PROGRAM com- be turned on as the SST89C54/58 enters External Host

mands are used for programming new data into the Mode; i.e. when PSEN# goes low while RST is high. The

memory array. Selection of which Program command to

use will be dependent upon the desired programming

oscillator provides both clocking for the Flash Control

Unit as well as timing references for Program and Erase

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field size. Programming will not take place if any security operations. During External Host Mode, the CPU core is

locks are enabled on the selected memory block.

The BYTE-PROGRAM command programs data into a

held in reset. Upon exit from External Host Mode, the

internal oscillator is turned off.

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single byte. Ports P0[7:0] are used for data in. The The same oscillator also provides the time base for the

memory location is selected by P1[7:0], P2[5:0], and

P3[5:4] (A15-A0). The BYTE-PROGRAM command is

watchdog timer and timing references for IAP Mode

Program and Erase operations. See more detailed de-

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selected by the binary code of 11b on P3[7:6] and 10b on scription in later sections.

P2[7:6]. See Figure 14 for timing waveforms.

Arming Command

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The BURST-PROGRAM command programs data to an

An arming command sequence must take place before

entire row, sequentially byte-by-byte. Ports P0[7:0] are

any External Host Mode sequence command is recog-

used for data in. The memory location is selected

nized by the SST89C54/58. This prevents accidental

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by P1[7:0], P2[5:0], and P3[5:4] (A15-A0). The BURST-

triggering of External Host Mode Commands due to

PROGRAM command is selected by the binary code of

noise or programmer error. The arming command is as

01b on P3[7:6] and 10b on P2[7:6]. See Figure 15 for

follows:

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timing waveforms.

1. PSEN# goes low while RST is high. This will get

The BYTE-VERIFY command allows the user to verify

that the SST89C54/58 correctly performed an Erase or

the machine in External Host Mode, re-configur-

ing the pins.

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Program command. Ports P0[7:0] are used for data out.

2. A Read-ID command is issued and held for 1 ms.

The memory location is selected by P1[7:0], P2[5:0], and

P3[5:4] (A15-A0). The BYTE-VERIFY command is se-

After the above sequence, all other External Host Mode

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lected by the binary code of 11b on P3[7:6] and 00b on

commands are enabled. Before the Read-ID command

P2[7:6]. This command will be disabled if any security

is received, all other External Host commands received

locks are enabled on the selected memory block. See

are ignored.

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Figure 16 for timing waveforms.

Programming a SST89C54/58

The PROG-SB1, PROG-SB2, PROG-SB3 commands

program the security bits, the functions of these bits are

To program data into the memory array, apply power

supply voltage (VDD) to VDD and RST pins, and perform

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described in a Security Lock section and also in Table 8.

the following steps:

Once programmed, these bits can only be cleared

through a CHIP-ERASE command.

1. Maintain RST high and toggle PSEN# from logic

high to low, in sequence per the appropriate timing

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diagram.

The PROG-RB1, and PROG-RB0 commands program

the Re-Map[1:0] bits. The Re-Map[1:0] bits determine

the Memory Re-mapping default option on reset. Upon

2. Raise EA# High (either VIH or VH).

3. Issue READ-ID command to enable the External

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completion of the Reset sequence, the MAP_EN[1:0]

Host Mode.

bits are initialized to the default value set by the Re-

Map[1:0] bits according to Table 2. Subsequent program

4. Verify that the memory blocks or sectors for pro-

gramming is in the erased state, FFh. If they are not

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manipulation of MAP_EN[1:0] bits will alter the Memory

erased, then erase them using the appropriate

Re-mapping option but will not change the Re-Map[1:0]

bits. Therefore, any changes to MAP_EN[1:0], without

Erase command.

5. Select the memory location using the address lines

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corresponding updates to Re-Map[1:0], will not survive a

(P1[7:0], P2[5:0], P3[5:4]).

Reset cycle.

6. Present the data in on P0[7:0].

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If an External Host Mode command, except for CHIP-

7. Pulse ALE/PROG#, observing minimum pulse

ERASE, is issued to a locked memory block, the device

width.

will ignore this command.

8. Wait for low to high transition on READY/BUSY#

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(P3[3]).

External Host Mode Clock Source

9. Repeat steps 5 – 8 until programming is finished.

In External Host Mode, an internal oscillator will provide

clocking for the SST89C54/58. The on-chip oscillator will

10. Verify the flash memory contents.

© 2000 Silicon Storage Technology, Inc.

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344-2 8/00

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