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UT69151-XTE5WCX View Datasheet(PDF) - Aeroflex UTMC

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UT69151-XTE5WCX Datasheet PDF : 177 Pages
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3.2 SBC Architecture
As defined in MIL-STD-1553, the bus controller initiates all
communications on the bus. To meet MIL-STD-1553 bus
controller requirements, the S IT utilizes a Command
Block architecture that takes advantage of both internal registers
and external memory. Each command word transmitted over the
bus must be associated with a Command Block. The Command
Block requires eight contiguous memory locations for each
message. These eight locations include a control word, two
command word locations, a data pointer, two status word
locations, a branch address location, and a timer value.
The host, or ROM for autonomous operation, must initialize
each of the locations associated with each Command Block (the
exception is for the two status locations which will be updated
as command words are transmitted and corresponding status
words are received). Figure 8 shows the SBC’s Command Block
architecture while Sections 3.2.1 through 3.2.6 describe each
location associated with the Command Block.
Control Word
Command Word 1
Command Word 2
Data Pointer
Status Word 1
Status Word 2
Branch Address
Timer Value
Figure 8. Command Block Definition
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