5962F9466311VXX View Datasheet(PDF) - Aeroflex UTMC
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5962F9466311VXX Datasheet PDF : 177 Pages
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2.0 REMOTE TERMINAL ARCHITECTURE
The SµMMIT Remote Terminal (SRT) is an interface device
linking a MIL-STD-1553 serial data bus to a host
microprocessor and/or subsystem. The SRT’s MIL-STD-1553
interface includes encoding/decoding logic, error detection,
command recognition, DMA interface, control/configuration
registers, clock, and reset logic. The following sections review
the architecture and use. Each section supplies information on
the SRT’s configuration and operation.
2.1 Register Descriptions
The following list provides the bit descriptions of the 32 internal
registers that control SRT operation. All register bits are active
high and reflect a logic zero condition (0000 hex) after Master
Reset (except those reflecting input pins).
Register
Number
0
1
2
3
4
5
6
7
8
9
10-15
16-31
Name
Control Register
Operational Status Register
Current Command Register
Interrupt Mask Register
Pending Interrupt Register
Interrupt Log List Pointer Register
BIT Word Register
Time-Tag Register
SRT Descriptor Pointer Register
1553 Status Word Bits Register
Not Applicable
Illegalization Registers
Register Address
0000 (hex)
0001 (hex)
0002 (hex)
0003 (hex)
0004 (hex)
0005 (hex)
0006 (hex)
0007 (hex)
0008 (hex)
0009 (hex)
000A to 000F (hex)
0010 to 001F (hex)
Note: Reference section 9.1.2 for SµMMIT XT 8-bit register address numbers.
2.1.1 Control Register (Read/Write) - Register 0
This 16-bit register controls SRT configuration. To make changes to the SRT and this register, the STEX bit (Bit 15 of the Control
Register) must be logic zero. Note: The user has 5µs after TERACT active to stop execution.
Bit
Number
Mnemonic
Description
15
STEX
Start Execution. Assertion of this bit initiates SµΜΜIT operation. A Control
Register write negating this bit inhibits SµΜΜIT operation. A remote terminal
address parity error prevents SRT operation regardless of the logical state of this
bit. If a RT address parity error exists, bit 3 of Register 1 will be set low and bit
2 of Register 1 will be set high.
14
SBIT
Start BIT. Assertion of this bit places the SµΜΜIT into the Built-In Test routine.
The BIT test has a fault coverage of 93.4%. If the SµΜΜIT has been started,
the host must halt the device in order to place the SµΜΜIT into the Built-In Test
routine (STEX = 0) (see section 8.0 for additional information).
Note: If Start BIT (SBIT) and Start Execution (STEX) are both set on one register
write, BIT has priority.
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SµMMIT FAMILY
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