59629475804QXC View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
59629475804QXC Datasheet PDF : 177 Pages
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3.1.6 Interrupt Log List Pointer Register (Read/Write) - Register 5
The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List. The Interrupt Log List is a 32-word ring-
buffer that contains information pertinent to the service of interrupts. The S IT architecture requires the location of the Interrupt
Log List on a 32-word boundary. The most significant 11 bits of this register designate the location of the Interrupt Log List within
a 64K memory space. Initialize the lower five bits of this register to a logic zero. The S IT controls the lower five bits to
implement the ring-buffer architecture. The host or subsystem reads this register to determine the location and number of interrupts
within the Interrupt Log List (least significant five bits).
Bit
Number
15-0
Mnemonic
INTA(15:0)
Description
Interrupt Log List Pointer Bits. These bits indicate the starting location of the Interrupt
Log List.
3.1.7 BIT Word Register (Read/Write) - Register 6
This register contains information on the current health of the SBC. The lower eight bits of this register are user-defined.
Bit
Number
15
14
13
12
11
10
9
8
7-0
Mnemonic
Description
DMAF
WRAPF
N/A
BITF
CHAF
CHBF
MSBF/UDB
LSBF/UDB
UDB (7:0)
DMA Fail. Assertion of this bit indicates that all DMA activity had not been completed
from the time DMAR asserts to when the timer decrements to zero (i.e., 16 s). The DMA
activity includes DMAR to DMAG, and all wait states. In the event of a DMA failure,
current processing terminates.
Wrap Fail. The SBC automatically compares the transmitted word (encoder word) to the
reflected decoder word by way of the continuous loop-back feature. If the encoder word
and reflected word do not match, the WRAPF bit asserts. The loop-back path is via the
MIL-STD-1553 bus transceiver.
Not Applicable.
BIT Fail. Assertion of this bit indicates a BIT failure. Interrogate bit 11 through 8 to
determine the specific failure.
Channel A Fail. Assertion of this bit indicates a BIT test failure in Channel A.
Channel B Fail. Assertion of this bit indicates a BIT test failure in Channel B.
Memory Test Fail. Most significant memory byte failure (S MMIT XT). User-Defined
Bits (S MMIT & S MMIT LX/DX).
Memory Test Fail. Least significant memory byte failure (S MMIT XT). User-Defined
Bits (S MMIT & S MMIT LX/DX).
User-Defined Bits.
3.1.8 Minor Frame Timer Register (Read-only) - Register 7
This register is loaded via the Minor Frame Timer (MFT) opcode (Opcode 1110). For user-defined resolution use TCLK. Register
resets to zero anytime operation halts.
Bit
Number
15-0
Mnemonic
MFT(15:0)
Description
Minor Frame Timer. These bits indicate the value of the Timer.
40
S MMIT FAMILY
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