3.1.5 Pending Interrupt Register (Read-only) - Register 4
This register is used to identify which of the interrupts occurred during operation. The assertion of any bit in this register asserts an
output pin, MSG_INT or YF_INT (three clock cycles). Writing to the most significant four bits of this register generates a YF_INT.
Bit
Number
15
14
13
12
11
10-6
5
4
3
2
1
0
Mnemonic
DMAF
WRAPF
N/A
BITF
MERR
N/A
EOL
ILLCMD
ILLOP
RTF
CBA
N/A
Description
DMA Fail Interrupt. Once the S IT has issued the DMAR signal, an internal timer
is started. If all DMA activity (which includes DMAR, DMAG, and all DTACK) has not
been completed, the interrupt is generated. In the SBC mode, the YF_INT interrupt is
generated (if not masked) and command processing stops.
Wrap Fail Interrupt. The SRT automatically compares the transmitted word (encoder
word) to the reflected decoder word by way of the continuous loop-back feature. If the
encoder word and reflected word do not match, the WRAPF bit asserts and the YF_INT
interrupt is generated (if not masked). The loop-back path is via the MIL-STD-1553 bus
transceiver.
Not Applicable.
BIT Fail Interrupt. Assertion of this bit indicates a BIT failure. Interrogate Bit Word
Register bits 11 and 10 to determine the specific failure. In SBC mode, the YF_INT
interrupt is generated (if not masked) and command processing stops if initiated by
opcode.
Message Error Interrupt. Assertion of this bit indicates the occurrence of a message error.
The SBC can detect Manchester, sync-field, word count, 1553 word parity, bit count, and
protocol errors. This bit will be set and an MSG_INT interrupt generated (if not masked)
after message processing is complete.
Not Applicable.
End Of List Interrupt. Assertion of this bit indicates that the SBC is at the end of the
command block. MSG_INT generated (if not masked).
Illogical Command Interrupt. Assertion of this bit indicates that an illogical command
(i.e., Transmit Broadcast or improperly formatted RT-RT message) was written into the
Command Block. The SBC checks for RT-RT Terminal address field match, RT-RT
transmit/receive bit mismatch and correct order, and broadcast transmit commands. If
illogical commands occur, the SBC will halt execution. MSG_INT generated (if not
masked).
Illogical Opcode Interrupt. Assertion of this bit indicates an illogical opcode (i.e., any
reserved opcode) was used in the command block. The SBC halts operation if this
condition occurs. MSG_INT generated (if not masked).
Retry Fail Interrupt. Assertion of this bit indicates all programmed retries failed.
MSG_INT generated (if not masked).
Command Block Accessed Interrupt. Assertion of this bit indicates a command block was
accessed (Opcode 1010), if enabled. MSG_INT generated (if not masked).
Not Applicable.
Note: The user must read or write a S MMIT register after reading the Pending Register to invoke the automatic clear of the Pending
Interrupt Register. For example, a Subaddress Access interrupt results in a Pending Interrupt Register of 040016. A read of the
Pending Interrupt Register returns a value of 040016. A subsequent read of the Interrupt Mask Register (i.e., Register 316), followed
by a Pending Interrupt Register read returns a value of 000016. The intervening read of the Interrupt Mask Register clears the Pending
Interrupt Register at the end of the Interrupt Mask Register read.
S MMIT FAMILY
39