3.1.3 Current Command Register (Read-only) - Register 2
This register contains the last 1553 command that was transmitted by the SBC. Upon the execution of each Command Block, this
register will automatically be updated. This register is updated when transmission of the Command Word begins. In a RT-RT transfer,
the register will reflect the latest Command Word as it is transmitted.
Bit
Number
15-0
Mnemonic
CC(15:0)
Description
Current Command. These bits contain the latest 1553 command that was transmitted by
the bus controller.
3.1.4 Interrupt Mask Register (Read/Write) - Register 3
The SBC interrupt architecture allows the host to mask or temporarily disable the service of interrupts. While masked, interrupt
activity does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for that event. An interrupt
is masked if the corresponding bit of this register is set to a logic zero.
Bit
Number
15
14
13
12
11
10-6
5
4
3
2
1
0
Mnemonic
DMAF
WRAPF
N/A
BITF
MERR
N/A
EOL
ILLCMD
ILLOP
RTF
CBA
N/A
Description
DMA Fail Interrupt.
Wrap Fail Interrupt.
Not Applicable.
BIT Fail Interrupt.
Message Error Interrupt.
Not Applicable.
End Of List Interrupt.
Illogical Command Interrupt.
Illogical Opcode Interrupt.
Retry Fail Interrupt.
Command Block Accessed Interrupt.
Not Applicable.
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