3.1.2 Operational Status Register (Read/Write) - Register 1
This register provides pertinent status information for the SBC and is not reset to 0000 (hex) on MRST. Instead, the register reflects
the actual stimulus applied to input pins MSEL(1:0), A/B STD, and LOCK. Assertion of the LOCK input prevents the modification
of the mode selects and the A or B standard bits. In this case, a write to this register’s most significant nine bits is meaningless. If
LOCK is negated, a read of this register reflects the information written into this register’s most significant nine bits.
Note: To make changes to the SBC and this register, the STEX bit (Register 0, bit 15) must be logic zero.
Bit Number
15-10
9
Mnemonic
N/A
MSEL(1)
8
MSEL(0)
7
A/B STD
6
LOCK
5
AUTOEN
4
N/A
3
EX
2
N/A
1
READY
0
TERACT
Description
Not Applicable.
Mode Select 1. In conjunction with Mode Select 0, this bit determines the S
of operation.
IT mode
Mode Select 0. In conjunction with Mode Select 1, this bit determines the S
of operation.
MSEL(1)
MSEL(0) Mode of Operation
0
0
Bus Controller = SBC
0
1
Remote Terminal = SRT
1
0
Monitor Terminal = SMT
1
1
SMT/SRT
IT mode
Military Standard 1553A or 1553B. This bit determines whether the SBC will operate
under MIL-STD-1553A or 1553B protocol. Assertion of this bit forces the SBC to look
for all responses in 9 s or generate time-out errors. Negation of this bit automatically
allows the SBC to operate under the MIL-STD-1553B protocol. See section 3.6 and
section 5.0, Enhanced S MMIT Family Operation, for additional information.
LOCK Pin. This read-only bit reflects the inverted state of the LOCK input pin and is
latched on the rising edge of MRST.
AUTOEN Pin. This read-only bit defines whether or not the auto enable feature will be
used in the design. This bit shows the inverse of the auto enable (AUTOEN) input pin.
Not Applicable.
S IT Executing. This read-only bit indicates whether the SBC is presently executing
or is idle. A logic one indicates that the S IT is executing; logic zero indicates the
S IT is idle.
Not Applicable.
READY Pin. This read-only bit reflects the inverted state of the output pin READY and
is cleared on reset.
TERACT Pin. Assertion of this bit indicates that the SBC is presently executing. This
read-only bit reflects the inverted state of output pin TERACT and is cleared on reset.
Note: When STEX transitions from 0 to 1, EX and TERACT stay active until command processing is complete.
S MMIT FAMILY
37