5962F9466311VXA View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F9466311VXA Datasheet PDF : 177 Pages
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3.1.1 Control Register (Read/Write)- Register 0
The Control Register’s function is to configure the S IT for operation. To make changes to the SBC and this register, the STEX
bit (Bit 15) must be logic zero. To operate the S IT as a bus controller (SBC), use the following bits.
Bit Number
15
Mnemonic
STEX
14
SBIT
13
12-11
10
SRST
N/A
ETCE
9
--
8-7
N/A
6
BUFR
5
N/A
4
BCEN
3
N/A
2
PPEN
1
INTEN
0
N/A
Description
Start Execution. Assertion of this bit commences operation of the S IT. A Control
Register write negating this bit inhibits operation of the S IT. After execution begins,
a write of logic zero will halt the SBC after completing the current opcode. Prior to halting,
the SBC determines the next command block pointer address and loads the value into
Register 8. For an EOL command block, Register 8 is not updated.
Start BIT. Assertion of this bit places the S IT into the Built-In Test routine. The BIT
test has a fault coverage of 93.4%. Once the S IT has been started, the host must halt
the device in order to place the S
the bit opcode.
IT into the Built-In Test routine (STEX = 0) or use
Note: If Start BIT (SBIT) and Start Execution (STEX) are both set on one register write,
BIT has priority.
Software Reset. Assertion of this bit immediately places the S IT into a software
reset. Like MRST, the software reset (which takes 5 s to execute) clears all internal logic.
Note: During auto-initialization, do not load this bit with a logic one. SRST will only
function after READYB is asserted.
Not Applicable.
External Timer Clock Enable. Assertion of this bit enables an external clock used with
an internal counter for variable minor frame timing.
Refer to section 3.1.8.
Note: The user can only change the clock frequency before starting the device (i.e., setting
bit 15 of Register 0 to a logic one).
See section 5, Enhanced S MMIT Family Operation, for additional information.
Not Applicable.
Buffer Mode Enable. Assertion of this bit enables the buffer mode of operation. Refer to
section 9.1.5 or 9.2.3 for additional information.
Not Applicable.
Broadcast Enable. Assertion of this bit enables the broadcast option for the SBC. Negation
of this bit enables the remote terminal address 31 as a unique RT address. When enabled,
the SBC does not expect a status word response from the remote terminal.
Not Applicable.
Ping-Pong Enable. This bit controls the method by which the SBC will retry messages.
A logic one allows the SBC to ping-pong between buses during retries. A logic zero
dictates that all retries will be performed on the programmed bus as defined in the
Command Block control word. (Section 3.2.1 of this document defines the retry bit).
Interrupt Log List Enable. Assertion of this bit enables the Interrupt Log List. Negation
of this bit prevents the logging of interrupts as they occur.
Not Applicable.
36
S MMIT FAMILY
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