5962F9211803QZC View Datasheet(PDF) - Aeroflex UTMC
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5962F9211803QZC Datasheet PDF : 177 Pages
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3.0 BUS CONTROLLER ARCHITECTURE
The S MMIT bus controller (SBC) is an interface device
linking a MIL-STD-1553 serial data bus to a host
microprocessor and/or subsystem. The SBC’s architecture is
based on a Command Block structure and internal,
programmable registers. Designed to run autonomously and
reduce host overhead, the SBC’s RISC-based core automatically
executes data handling, message error checking, memory
control, and related protocol functions. This section discusses
the following SBC features and functions:
Multiple Message Processing
Message Scheduling
Polling Capability
Executable Architecture
Built-In Test
Interrupt Structure
Memory Management
3.1 Register Descriptions
To initialize the S IT as a bus controller, the designer must
understand the internal registers. The SBC registers offer many
programmable functions and allow host access to extensive
information. All register bits are active high and reflect a logic
zero condition (0000 hex) after Master Reset (except those
reflecting input pins). Each register associated with the bus
controller mode of operation is individually described below.
Register Number
0
1
2
3
4
5
6
7
8
9
10
11-31
Name
Control Register
Operational Status Register
Current Command Block Register
Interrupt Mask Register
Pending Interrupt Register
Interrupt Log List Pointer Register
BIT Word Register
Minor-Frame Timer
Command Block Pointer Register
Not Applicable
BC Command Block Initialization Count Register
Not Applicable
Note: Reference section 9.1.2 for S MMIT XT 8-bit register address numbers.
Register Address
0000 (hex)
0001 (hex)
0002 (hex)
0003 (hex)
0004 (hex)
0005 (hex)
0006 (hex)
0007 (hex)
0008 (hex)
0009 (hex)
000A (hex)
000B to 001F (hex)
S MMIT FAMILY
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