5962F9466309VXA View Datasheet(PDF) - Aeroflex UTMC
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5962F9466309VXA Datasheet PDF : 177 Pages
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2.2.4 Mode Code Transmit Control Word
The following bits describe the transmit mode code Descriptor Control Word. Information contained in this word assists the SRT
in message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SRT during command
post-processing.
Note: In MIL-STD-1553A, all mode codes are without data, and the T/R bit is ignored. See section 2.9 for the MIL-STD-1553A
operation.
Bit
Number
Mnemonic
Description
15-7
N/A
Not Applicable.
6
IWA
Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when
mode code command is received. The interrupt is entered into the Pending Interrupt
Register if not masked in the Mask Register. Output pin MSG_INT asserts after message
processing.
5
IBRD
Interrupt Broadcast Received. Assertion of this bit enables the generation of an interrupt
when a valid broadcast mode code is received. The interrupt is entered into the Pending
Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after
message processing.
4
BAC
Block Accessed. The subsystem or host initializes this bit to zero; the SRT overwrites the
zero with a logic one upon completion of message processing. After interrogating this
bit, the host resets this bit to zero to observe further accesses.
3
N/A
Not Applicable.
2
A/B
Buffer A/B. This bit indicates the last buffer accessed when buffer ping-pong is enabled.
During initialization, the host designates the first buffer used by asserting or negating this
bit. A logic one indicates buffer A; a logic zero indicates buffer B. This bit is a “don’t
care” if buffer ping-ponging is not enabled.
1
BRD
Broadcast Received. Assertion of this bit indicates the reception of a broadcast command.
0
N/A
Not Applicable.
24
SµMMIT FAMILY
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