5962F9211804VXA View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F9211804VXA

Enhanced SuMMIT XTE MIL-STD-1553 dual redundant bus controller/remote terminal/monitor/transceiver multichip module SMD. Lead finish gold. Class Q. Device type 09 (SuMMIT XTE 5V/12V). Radiation none.

Aeroflex UTMC 

2.2.3 Mode Code Receive Control Word

The following bits describe the receive mode code Descriptor Control Word. Information contained in this word assists the SRT in

message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SRT during command

post-processing.

Note: In MIL-STD-1553A, all mode codes are without data, and the T/R bit is ignored. See section 2.9 for the MIL-STD-1553A

operation.

Bit

Number

Mnemonic

Description

15-8

INDX

Index Field. These bits define message buffer length. The host or subsystem uses this

field to instruct the SRT to buffer “N” messages. “N” can range from 0 (00 hex) to 256

(FF hex). If buffer ping-ponging is enabled, the INDX field is “don’t care” (i.e., does not

contain applicable information). The SRT does not perform message buffering in the ping-

pong mode of operation. The index decrements each time a complete message is transacted

(no message errors). The index does not decrement if the mode code is illegalized. The

SRT can generate an interrupt when the index field transitions from one to zero (see bit 7).

7

INTX

Interrupt Index Equals Zero. Assertion of this bit enables the generation of an interrupt

when the index field transitions from one to zero. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

6

IWA

Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when

mode code command is received. The interrupt is entered into the Pending Interrupt

Register if not masked in the Mask Register. Output pin MSG_INT asserts after message

processing.

5

IBRD

Interrupt Broadcast Received. Assertion of this bit enables the generation of an interrupt

when a valid broadcast mode code command is received. The interrupt is entered into the

Pending Interrupt Register if not masked in the Mask Register. Output pin MSG_INT

asserts after message processing.

4

BAC

Block Accessed. The subsystem or host initializes this bit to zero; the SRT overwrites the

zero with a logic one upon completion of message processing. After interrogating this

bit, the host resets this bit to zero to observe further accesses.

3

N/A

Not Applicable.

2

A/B

Buffer A/B. Indicates the last buffer accessed when buffer ping-pong is enabled. During

initialization, the host designates the first buffer used by asserting or negating this bit. A

logic one indicates buffer A; logic zero indicates buffer B. This bit is a “don’t care” if

buffer ping-ponging is not enabled.

1

BRD

Broadcast Received. Assertion of this bit indicates the reception of a valid broadcast

command.

0

NII

Notice II. Asserting this bit enables the use of the Broadcast Data Pointer as a buffer for

broadcast command information. When negated, broadcast information is stored in the

same buffer as non-broadcast information.

SµMMIT FAMILY

23

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