5962F9466308VYA View Datasheet(PDF) - Aeroflex UTMC
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5962F9466308VYA Datasheet PDF : 177 Pages
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2.1.6 Interrupt Log List Pointer Register (Read/Write) - Register 5
The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List. The Interrupt Log List is a 32 word ring-
buffer that contains information pertinent to the service of interrupts. The SµΜΜIT architecture requires the location of the Interrupt
Log List on a 32-word boundary. The most significant 11 bits of this register designate the location of the Interrupt Log List within
a 64K memory space. The lower 5 bits of this register should be initialized to a logic zero. The SµΜΜIT controls the lower 5 bits
to implement the ring-buffer architecture. The host or subsystem reads this register to determine the location and number of interrupts
within the Interrupt Log List (least significant 5 bits).
Note: Bits 15-5 indicate the starting Base address while bits 4-0 indicate the ring location of the Interrupt Log List. See section 6.0
for a description of the Interrupt Architecture.
Bit
Number
15-0
Mnemonic
Description
INTA(15:0) Interrupt Log List Pointer Bits. (Bit 15 MSB - Bit 0 LSB).
2.1.7 BIT Word Register (Read/Write) - Register 6
This register contains information on the SRT’s current health. The SRT transmits the contents of this register upon reception of a
Transmit Bit Word Mode Code. The lower 8 bits of this register are user-defined.
Bit
Number
Mnemonic
Description
15
DMAF
DMA Fail. This bit is set if all DMA activity is not completed between the time DMAR
asserts and when the timer decrements to zero. The DMA activity includes DMAR to
DMAG and all wait states. In the event of a DMA failure, current message processing
terminates; remote terminal waits for next 1553 message.
14
WRAPF
Wrap Fail. The SRT automatically compares the transmitted word
(encoder word) to the reflected decoder word via the continuous loop-back feature. If the
encoder word and reflected word do not match, the WRAPF bit asserts and a YF_INT
interrupt is generated (if not masked). The loop-back path is via the MIL-STD-1553 bus
transceiver. A wrap failure does not result in the terminal flag bit being set to a logical
one. Message processing continues.
13
TAPF
Terminal Address Parity Fail. This bit reflects the outcome of the remote terminal address
parity check. A logic one indicates a parity failure. When a parity error occurs the SRT
does not begin operation (STEX bit forced to a logic zero), channel A and B do not enable,
and a YF_INT interrupt is generated (if not masked).
12
BITF
BIT Fail. Assertion of this bit indicates a BIT failure. Bits 11 through 8 should be
interrogated to determine the specific failure. Status word bit 19 is automatically set to a
logic one when a BIT failure occurs. If a BIT fails, the BITF bit is asserted, and a YF_INT
interrupt is generated (if not masked). Operation continues.
11
CHAF
Channel A Fail. Assertion of this bit indicates a BIT test failure in Channel A.
10
CHBF
Channel B Fail. Assertion of this bit indicates a BIT test failure in Channel B.
9
MSBF/UDB Memory Test Fail. Most significant memory byte failure (SµMMIT XT). User-Defined
Bits (SµMMIT & SµMMIT LX/DX).
8
LSBF/UDB Memory Test Fail. Least significant memory byte failure (SµMMIT XT). User-Defined
Bits (SµMMIT & SµMMIT LX/DX).
7-0
UDB(7:0)
User-Defined Bits.
12
SµMMIT FAMILY
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