5962F9466309VXA View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F9466309VXA Datasheet PDF : 177 Pages
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Bit
Number
15
14
13
12
11
10
9
8
7
6-0
Mnemonic
DMAF
WRAPF
TAPF
BITF
MERR
SUBAD
BDRCV
IXEQ0
ILLCMD
N/A
Description
DMA Fail Interrupt. Once the SµΜΜIT issues the DMAR signal, an internal timer starts.
If all DMA activity (which includes DMAR to DMAG, and all wait states) is not
completed by the time the counter decrements to zero, the interrupt is generated. In the
SRT mode, the YF_INT interrupt is generated (if not masked), current command
processing ends, and the SRT will remain on-line. Current cycle terminated, bus released.
Wrap Fail Interrupt. The SRT automatically compares the transmitted word (encoder
word) to the reflected decoder word via the continuous loop-back feature. If the encoder
word and reflected word do not match, the WRAPF bit is asserted in the BIT Word Register
and a YF_INT interrupt is generated (if not masked). The loop-back path is via the MIL-
STD-1553 bus transceiver.
Terminal Address Parity Fail Interrupt. This bit reflects the outcome of the remote terminal
address parity check. A logic one indicates a parity failure. When a parity error occurs,
the SRT does not begin operation (STEX bit forced to logic zero), channel A and B do
not enable, the TAPF bit is asserted here and in the BIT Word Register, and a YF_INT
interrupt is generated (if not masked).
BIT Fail Interrupt. Assertion of this bit indicates a BIT failure. Status word bit 19 is
automatically set to a logic one when a BIT failure occurs. If a BIT fails, the BITF bit is
asserted here and in the BIT Word Register, and a YF_INT interrupt is generated (if not
masked). Operation continues.
Message Error Interrupt. Assertion of this bit indicates that a message error condition
exists. The SRT can detect Manchester errors, sync-field, word count errors (too many
or too few), MIL-STD-1553 word parity errors, bit count errors (too many or too few),
and protocol errors. If not masked, this bit is always set when the SRT asserts bit 9 of the
status word (e.g., illegal commands, invalid data word, etc.). MSG_INT interrupt
generated (if not masked).
Subaddress Accessed Interrupt. Assertion of this bit indicates a pre-selected subaddress
has transacted a message. To determine the exact subaddress, the host interrogates the
interrupt log IAW. MSG_INT interrupt generated (if not masked).
Broadcast Command Received Interrupt. This bit is set to a logic one to indicate the SRT’s
receipt of a valid broadcast command. The SRT suppresses status word transmission.
MSG_INT interrupt generated (if not masked).
Index Equal Zero Interrupt. The SRT asserts this bit to indicate the completion of a pre-
defined number of commands by the SRT. Upon assertion of this interrupt, the host or
subsystem updates the subaddress descriptor to prevent the potential loss of data.
MSG_INT interrupt generated (if not masked).
Illegal Command Interrupt. This bit is set to a logic one to indicate the reception of an
illegal command by the SRT. Upon receipt of this command, the SRT responds with a
status word only; Bit 9 of the status word is set to a logic one. MSG_INT interrupt
generated (if not masked).
Not Applicable.
Note: The user must read or write a SµMMIT register after reading the Pending Register to invoke the automatic clear of the
Pending Interrupt Register. For example, a Subaddress Access interrupt results in a Pending Interrupt Register of 040016. A
read of the Pending Interrupt Register returns a value of 040016. A subsequent read of the Interrupt Mask Register (i.e., Register
3), followed by a Pending Interrupt Register read returns a value of 000016. The intervening read of the Interrupt Mask Register
clears the Pending Interrupt Register at the end of the Interrupt Mask Register read.
SµMMIT FAMILY
11
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