2.1.4 Interrupt Mask Register (Read/Write) - Register 3
The SRT interrupt architecture allows for the masking of all interrupts. An interrupt is masked if the corresponding bit of this register
is set to logic zero. This feature allows the host or subsystem to temporarily disable the service of interrupts. While masked, interrupt
activity does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for that event.
Bit
Number
Mnemonic
Description
15
DMAF
DMA Fail Interrupt
14
WRAPF
Wrap Fail Interrupt
13
TAPF
Terminal Address Parity Fail Interrupt
12
BITF
BIT Fail Interrupt
11
MERR
Message Error Interrupt
10
SUBAD
Subaddress Accessed Interrupt
9
BDRCV
Broadcast Command Received Interrupt
8
IXEQ0
Index Equal Zero Interrupt
7
ILLCMD
Illegal Command Interrupt
6-0
N/A
Not Applicable+
2.1.5 Pending Interrupt Register (Read-only) - Register 4
The Pending Interrupt Register contains information that identifies events that generate interrupts. The assertion of any bit in this
register asserts an output pin, MSG_INT or YF_INT (three clock cycles). Writing to the most significant 4 bits of this register
generates a YF_INT.
.
10
SµMMIT FAMILY