RTL8196C
Datasheet
7. Peripheral and MISC Control
7.1. GPIO Control
The RTL8196C provides four sets of General Purpose Input/Output (GPIO) pins (GPIO A, B, C, D).
Each GPIO pin may be configured as an input or output pin. The GPIO DATA register may be used to
control GPIO pin signals. The GPIO pins are shared with some peripheral pins, and the type of peripheral
can affect the attributes of the shared pins. All GPIO sets can be used to generate interrupts, and an
interrupt mask and status register are provided. All the GPIO control registers are defined in the following
tables.
7.1.1. GPIO Register Set (0xB800_3500)
Offset
0x00
0x08
k 0x0C
0x10
lte 0x14
0x18
Size (byte)
4
4
4
4
4
4
Table 13. GPIO Register Set (0xB800_3500)
Name
Description
PABCD_CNR
Port A, B, C, D Control Register
PABCD_DIR
Port A, B, C, D Direction Register
PABCD_DAT
Port A, B, C, D Data Register
PABCD_ISR
Port A, B, C, D Interrupt Status Register
PAB_IMR
Port A, B Interrupt Mask Register
PCD_IMR
Port C, D Interrupt Mask Register
a IAL 7.1.2. GPIO Port A, B, C, D Control Register (PABCD_CNR)
T (0xB800_3500)
Re EN ION Bit
T 31:24
ID A 23:16
R 15:8
NF RPO 7:0
Table 14. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)
Name
Description
RW
PFC_D[7:0] Pin Function Configuration of Port D
RW
PFC_C[7:0] Pin Function Configuration of Port C
RW
PFC_B[7:0] Pin Function Configuration of Port B
RW
PFC_A[7:0] Pin Function Configuration of Port A
RW
Bit Value:
0: Configured as GPIO pin
1: Configured as dedicated peripheral pin
CO CO 7.1.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR)
TE (0xB800_3508)
Z Table 15. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800_3508)
for Bit
Name
Description
RW
Default
FFH
FFH
FFH
FFH
Default
n.31-n.24 DRC_D[7:0] Pin Direction Configuration of Port D
RW
00H
0: Configured as input pin
1: Configured as output pin
n.23-n.16 DRC_C[7:0] Pin Direction Configuration of Port C
RW
00H
0: Configured as input pin
1: Configured as output pin
n.15-n.8 DRC_B[7:0] Pin Direction Configuration of Port B
RW
00H
0: Configured as input pin
1: Configured as output pin
n.7-n.0
DRC_A[7:0] Pin Direction Configuration of Port A
RW
00H
0: Configured as input pin
1: Configured as output pin
IEEE 802.11n AP/Router Network Processor with EEE 20
Track ID: JATR-2265-11 Rev. 0.7