5962F0153501VXC View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F0153501VXC Datasheet PDF : 13 Pages
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RECEIVER SWITCHING CHARACTERISTICS1
(VDD = 3.0V to 3.6V; TA = -55°C to +125°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
CLHT3 CMOS/TTL Low-to-High Transition Time (Figure 5)
3.5
ns
CHLT3 CMOS/TTL High-to-Low Transition Time (Figure 5)
3.5
ns
RSPos0 3
RSPos1 3
Receiver Input Strobe Position for Bit 0 (Figure 10)
Receiver Input Strobe Position for Bit 1 (Figure 10)
f=50MHz
f=50MHz
0.59
1.33
ns
3.45
4.19
ns
RSPos23 Receiver Input Strobe Position for Bit 2 (Figure 10) f=50MHz
6.30
7.04
ns
RSPos3 3
RSPos4 3
RSPos5 3
RSPos6 3
RCOP3
Receiver Input Strobe Position for Bit 3 (Figure 10)
Receiver Input Strobe Position for Bit 4 (Figure 10)
Receiver Input Strobe Position for Bit 5 (Figure 10)
Receiver Input Strobe Position for Bit 6(Figure 10)
RxCLK OUT Period (Figure 6)
f=50MHz
f=50MHz
f=50MHz
f=50MHz
f=50MHz
9.16
9.90
ns
12.02
12.76
ns
14.88
15.62
ns
17.73
18.47
ns
20.00
66.7
ns
RCOH3
RCOL 3
RSRC4
RHRC4
RCCD2
RxCLK OUT High Time (Figure 6)
RxCLK OUT Low Time (Figure 6)
RxOUT Setup to RxCLK OUT (Figure 6)
RxOUT Hold to RxCLK OUT (Figure 6)
RxCLK IN to RxCLK OUT Delay (Figure 7)
f=50MHz
f=50MHz
f=50MHz
f=50MHz
3.6
ns
3.6
ns
3.5
ns
3.5
ns
3.4
8.3
ns
RRLLS Receiver Phase Lock Loop Set (Figure 8)
10
ms
RPDD Receiver Powerdown Delay (Figure 9)
2
µs
Notes:
1. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and
max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and source clock jitter less than 250 ps (calculated from TPOS - RPOS) - see Figure 11.
2. Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and r eceiver (RCCD). The total latency for
LVDS217 Serializer and the LVDS218 Deserializer is (T + TCCD) + 2*T + RCCD), where T = Clock period.
3. Guaranteed by characterization.
4. Guaranteed by design.
5
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