5962F0153501VXA View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F0153501VXA Datasheet PDF : 13 Pages
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RxOUT 17
RxOUT 18
GND
RxOUT 19
RxOUT 20
N/C
LVDS GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
LVDS V DD
LVDS GND
RxIN2-
RxIN2+
RxCLK IN-
RxCLK IN+
LVDS GND
PLL GND
PLL V DD
PLL GND
PWR DWN
RxCLK OUT
RxOUT0
1
48
2
47
3
46
4
45
5
44
6
43
7
UT54LVDS218
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
TxIN
0
1
2
Figure 2. UT54LVDS218 Pinout
TX
VDD
PIN DESCRIPTION
RxOUT 16
RxOUT 15
Pin Name I/O No.
Description
RxOUT 14
GND
RxOUT 13
VDD
RxIN+
RxIN-
RxOUT
I
3 Positive LVDS differential data inputs1
I
3 Negative LVDS differential data output 1
O 21 TTL level data outputs
RxOUT 12
RxOUT 11
RxOUT 10
GND
RxCLK IN+
I
RxCLK IN-
I
RxCLK OUT O
1 Positive LVDS differential clock input
1 Negative LVDS differential clock input
1 TTL level clock output. The rising edge acts
as data strobe. Pin name RxCLK OUT.
RxOUT 9
VDD
RxOUT 8
RxOUT 7
RxOUT 6
GND
PWR DWN
VDD
GND
PLL VDD
I
1 TTL level input. When asserted (low input)
the receiver outputs are low
I
4 Power supply pins for TTL outputs and log-
ic
I
5 Ground pins for TTL outputs and logic
I
1 Power supply for PLL
RxOUT 5
RxOUT 4
RxOUT 3
PLL GND
LVDS V DD
I
2 Ground pin for PLL
I
1 Power supply pin for LVDS pins
VDD
LVDS GND
I
3 Ground pins for LVDS inputs
RxOUT 2
Notes:
RxOUT 1
1. These receivers have input fail-safe bias circuitry to guarantee a stable receiver
GND
output for floating or terminated receiver inputs. Under these conditions receiver
inputs will be in a HIGH state. If a clock signal is present, outputs will all be
HIGH; if the clock input is also floating/terminated outputs will remain in the
last valid state. A floating/terminated clock input will result in a LOW clock
output.
LVDS CABLE
MEDIA DEPENDENT DATA
(LVDS)
RX
RxOUT
0
1
2
CMOS/
TTL
18
19
20
TxCLK
PCB
CLOCK
(LVDS)
GND
SHIELD
Figure 3. UT54LVDS218 Typical Application
2
PCB
18
19
20
RxCLK
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