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X1226S8I View Datasheet(PDF) - Xicor -> Intersil

Part Name
Description
Manufacturer
X1226S8I
Xicor
Xicor -> Intersil Xicor
X1226S8I Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
X1226
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
1
1
0
1
1
0
0
1
1
1
Slave Address Byte
1
R/W Byte 0
Word Address 1
0
0
0
0
0
0
0
A8 Byte 1
Word Address 0
A7
A6
A5
A4
A3
A2
A1
A0
Byte 2
Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Byte 3
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
Figure 7. Byte Write Sequence
receipt of each address byte, the X1226 responds with
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 7.
Signals from
the Master
SDA Bus
Signals From
The Slave
S
t
a
r
Slave
t Address
Word
Address 1
Word
Address 0
S
t
o
Data
p
1
1 110 0000000
A
A
A
A
C
C
C
C
K
K
K
K
Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
Address
=6
REV 1.1.24 1/13/03
Address Pointer
Ends Here
Addr = 7
Address
40
www.xicor.com
23 Bytes
Address
63
Characteristics subject to change without notice. 10 of 24
 

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