A(18:0)
tAVAV
DQn(7:0)
Previous Valid Data
Assumptions:
1 . En and G < VIL (max) and Wn > V IH (min)
tA X Q X
Valid Data
tAVQV
Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0)
En
D Qn (7:0)
tETQV
tETQX
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable -Controlled Access
A(18:0)
tAVQV
G
DQn(7:0)
Assumptions:
1 . En < VIL (max) andW n > VIH (min)
tGLQX
tGLQV
DATA VALID
tG H Q Z
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
7