QL6325-5PT208M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6325-5PT208M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

I/O Cell Structure

Eclipse features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-

directional I/O pins and input-only pins. All I/O pins are 2.5 V and 3.3 V tolerant and comply with the specific

I/O standard selected. All dedicated input pins are 2.5 V tolerant and comply with the LVCMOS2 standard.For

single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced

I/O standards (e.g., SSTL), the voltage supplied to the INREF pins in each bank specifies the input switch

point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. Eclipse can

also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 6).

I/O

Standard

LVTTL

LVCMOS2

PCI

GTL+

SSTL3

SSTL2

Table 6: I/O Standards and Applications

INREF Reference

Voltage

n/a

n/a

Output Voltage

3.3

2.5

Application

General Purpose

General Purpose

n/a

3.3

PCI Bus Applications

1.0

n/a

Backplane

1.5

3.3

SDRAM

1.25

2.5

SDRAM

As designs become more complex and requirements more stringent, several application-specific I/O standards

have emerged for specific applications. I/O standards for processors, memories, and a variety of bus

applications have become commonplace and a requirement for many systems. In addition, I/O timing has

become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse

has addressed these new system requirements and now includes a completely new I/O cell which consists of

programmable I/Os as well as a new cell structure consisting of three registers—Input, Output, and Output

Enable (OE).

Eclipse offers banks of programmable I/Os that address many of the bus standards that are popular today. As

shown in Figure 6 each bi-directional I/O pin is associated with an I/O cell which features an input register,

an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one

output multiplexers.

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