QL6325-5PT208M View Datasheet(PDF) - QuickLogic Corporation
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QL6325-5PT208M Datasheet PDF : 73 Pages
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Eclipse Family Data Sheet Rev. F
RAM Modules
The Eclipse Family includes multiple dual-port 2,304-bit RAM modules for implementing RAM, ROM and
FIFO functions. Each module is user-configurable into four different block organizations. Modules can also be
cascaded horizontally to increase their effective width or vertically to increase their effective depth as shown
in Figure 3. The RAM can also be configured as a modified Harvard Architecture, similar to those found in
DSPs.
Figure 3: 2,304-bit Eclipse RAM Module
MODE[1:0] ASYNCRD
WA[9:0]
RA[9:0]
WD[17:0]
RD[17:0]
WE
RE
WCLK
RCLK
The number of RAM modules varies from 20 to 36 blocks within the Eclipse family, for a total of 46.1 to 82.9
K bits of RAM. Using two “mode” pins, designers can configure each module into 128 x 18 (Mode 0), 256 x
9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily cascadable to increase
their effective width and/or depth. See Figure 4.
Figure 4: Cascaded RAM Modules
WDATA
WADDR
RAM
Module
(2,304 bits)
RDATA
RADDR
WDATA
RAM
Module
(2,304 bits)
RDATA
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 1024 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
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