Eclipse Family Data Sheet Rev. F
Pin Descriptions
Table 23 describes the pins/balls of all Eclipse devices.
Table 23: Dedicated Pin Descriptions
Pin
Direction Function
Description
CLKa
Low skew global clock. This pin provides access to a dedicated,
I
Global clock distributed network capable of driving the CLOCK, SET, RESET, F1, and
network driver A2 inputs to the Logic Cell, READ and WRITE CLOCKS, Read and Write
Enables of the Embedded RAM Blocks, and Output Enables of the I/Os.
I/O(A)
The I/O pin is a bi-directional pin, configurable to either an input-only,
I/O
Input/Output
pin
output-only, or bi-directional pin. The A inside the parenthesis means that
the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool)
provides the option of tying that pin to GND, VCC, or TriState during
programming.
VCC
I
Power supply
pin
Connect to 2.5 V supply.
VCCIO(A)
VCCPLLb
This pin provides the flexibility to interface the device with either a 3.3 V
I
Input voltage
tolerance pin
device or a 2.5 V device. The A inside the parenthesis means that VCCIO is
located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input
signals and will output VCCIO level signals. This pin must be connected to
either 3.3 V or VCC.
I
Phase locked
loop power
supply pin
Connect to 2.5 V supply. VCCPLL should be connected to 2.5 V supply if
the PLLs are used. If the PLLs are not used, VCCPLL can be connected to
2.5 V supply or GND. See Table 11 for ICC differences when VCCPLL is
connected to 2.5 V or GND.
GND
PLLINa
I
Ground pin
Connect to ground.
I
PLL clock input Clock input for PLL.
DEDCLKa
I
Dedicated
clock pin
Low skew global clock. This pin provides access to a dedicated,
distributed clock network capable of driving the CLOCK inputs of all
sequential elements of the device (e.g., RAM and flip-flops).
GNDPLL
I
Ground pin for
PLL
Connect to GND.
INREF(A)
PLLOUTb
I
Differential
reference
voltage
The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3
standards. Follow the recommendations provided in Table 18 for the
appropriate standard. The A inside the parenthesis means that INREF is
located in BANK A. This pin should be tied to GND if not needed.
O
PLL output pin Dedicated PLL output pin. Otherwise may be left unconnected.
PLLRSTa
I
Reset input pin Reset input for PLL. If PLLs are not used, PLLRST should be connected
for PLL
to the same voltage as VCCPLL (e.g., VCC or GND).
This pin provides fast RESET, SET, CLOCK, and ENABLE access to the
I/O cell flip-flops, providing fast clock-to-out and fast I/O response times.
IOCTRL(A)a
I
Highdrive input This pin can also double as a high-drive pin to the internal logic cells. The
A inside the parenthesis means that IOCTRL is located in Bank A. This pin
should be tied to GND or VCC if it is not used.
a. All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped to the VCC rail, not the VCCIO.
Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V).
b. All PLLOUT output pins are driven by the VCC rail, not the VCCIO rail. These output pins are LVCMOS2 compliant only (2.5 V).
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