QL6325-6PT208C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6325-6PT208C

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Table 1: Eclipse Product Family Members

Max Gates

Logic Array

QL6250

248,160

40x24

QL6325

320,640

48x32

Logic Cells

Max Flip-Flops

Max I/O

960

2,670

250

1,536

4,002

310

RAM Modules

RAM bits

PQFP

20

46,100

208

24

55,300

208

PBGA (1.27 mm)

-

-

Packages

FPBGA (1.0 mm)

484

484

LFBGA (0.8 mm)

280

280

QL6500

488,064

64x48

3,072

7,185

347

32

73,700

-

516

484

280

QL6600

583,008

72x56

4,032

9,105

347

36

82,900

-

516

484

280

Device

QL6250

QL6325

QL6500

QL6600

Table 2: Max I/O per Device /Package Combination

208 PQFP

99

99

280 FPBGA

163

163

484 PBGA

250

310

-

163

327

-

163

327

516 PBGA

-

-

347

347

QuickWorks Design Software

The QuickWorks® package provides the most complete ESP and FPGA software solution from design entry

to logic synthesis, to place and route to simulation. The packages provide a solution for designers who use

third party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic and other third-party tools for design

entry, synthesis, or simulation.

Process Data

Eclipse is fabricated on a 0.25 μm five-layer metal CMOS process. The core voltage is 2.5 V VCC supply and

3.3 V tolerant I/O with the addition of 3.3 V VCCIO. Eclipse is available in commercial, industrial, and military

temperature grades.

Programmable Logic Architectural Overview

The Eclipse logic cell structure is presented in Figure 2. This architectural feature addresses current register-

intensive designs.

2

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www.quicklogic.com

© 2007 QuickLogic Corporation

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