QL6325-5PT208M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6325-5PT208M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Figure 20: Eclipse Global Clock Structure

Quad net

Clock Segment

tPGCK

tBGCK

Table 14: Eclipse Global Clock Tree Delays

Parameter

Global clock pin delay to quad net

Global clock buffer delay (quad net to flip flop)

Max. Rise

0.990 ns

0.534 ns

Value

Max. Fall

1.386 ns

1.865 ns

Figure 21: Global Clock Structure Schematic

Programmable Clock

Global Clock Buffer

External Clock

Global Clock

tPGCK

Clock

Select

tBGCK

© 2007 QuickLogic Corporation

www.quicklogic.com

•

•••

••

23

Share Link: