QL6325 View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6325

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Programmable Logic Routing

Eclipse devices are delivered with six types of routing resources as follows: short (sometimes called segmented)

wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the

length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two

logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and

GND (Logic ‘1’ and Logic ‘0’) to each column of logic cells.

Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically

used to implement intermediate length or medium fan-out nets.

Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher

capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the

length of the device. The resistance is lower because the express wires do not require the use of “pass” links.

Express wires provide higher performance for long routes or high fan-out nets.

Distributed networks are described in the clock/control section. These wires span the programmable logic and

are driven by “column clock” buffers. All clock network pin buffers (Dedicated and Global) are hard wired to

individual sets of column clock buffers.

Global POR (Power-On Reset)

The Eclipse family of devices features a global power-on reset. This reset is hardwired to all registers and resets

them to Logic ‘0’ upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-

flops has priority over the Set input. Therefore, the Global POR resets all flip-flops during power-up. If you

want to set the flip-flops to Logic ‘1’, you must assert the “Set” signal after the Global POR signal has been

deasserted.

Figure 12: Power-On Reset

VCC

Power-on

Reset

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