QL6325-4PS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6325-4PS484M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

For registered control operation, the array logic drives the D input of the OE cell register which in turn drives

the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered

signal to be driven to the three-state control.

When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to

be used for registered feedback into the logic array.

I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular

routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/Os. The

CLK and RESET signals share common lines, while the clock enables for each register can be independently

controlled. I/O interface support is programmable on a per bank basis. Figure 7 illustrates the I/O bank

configurations.

Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply

inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to

which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and

INREF can be shared within the same bank (e.g., PCI and LVTTL).

VCCIO 0

Figure 7: Multiple I/O Banks

INREF 0

VCCIO 1

INREF 1

VCCIO 7

PLL

Embedded RAM Blocks

PLL

VCCIO 2

INREF 7

VCCIO 6

INREF 6

PLL

VCCIO 5

Fabric

Embedded RAM Blocks

INREF 5

VCCIO 4

INREF 2

PLL

VCCIO 3

INREF 3

INREF 4

10

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© 2007 QuickLogic Corporation

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