AD7244JR View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7244JR

LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs

Analog Devices 

AD7242/AD7244

AD7242/AD7244 to TMS320C25 Interface

Figure 9 shows a serial interface between the AD7242/AD7244

and the TMS320C25 DSP processor. In this interface, the

CLKX and FSX signals of the TMS320C25 are generated from

the clock/timer circuitry. The FSX pin of the TMS320C25

must be configured as an input. CLKX is used to provide both

the TCLKA and TCLKB inputs of the AD7242/AD7244. DX

of the TMS320C25 is also routed to the serial data line of each

input port of the AD7242/AD7244.

output of one of the DACs will be updated on the sixteenth

falling edge of TXD after the respective TFS signal for that

DAC has gone low. Alternatively, the scheme used in previous

interfaces, whereby the LDAC inputs are driven from a timer,

can be used.

Data from the TMS32020 is valid on the falling edge of CLKX

after FSX goes low. This FSX signal is gated with the DACA/

DACB control line to determine whether TFSA or TFSB goes

low when FSX goes low.

The clock/timer circuitry also generates the LDAC signal for the

AD7242/AD7244 to synchronize the update of the outputs with

the serial transmission. As in the previous interface diagrams, a

common LDAC input is shown driving the LDACA and

LDACB inputs of the AD7242/AD7244. Once again, these

LDAC inputs could be hardwired low, in which case VOUTA or

VOUTB will be updated on the sixteenth falling edge of CLKX

after the TFSA or TFSB input goes low.

Figure 10. AD7242/AD7244 to 87C51 Interface

AD7242/AD7244 to 68HC11 Interface

Figure 11 shows a serial interface between the AD7242/AD7244

and the 68HC11 microcontroller. SCK of the 68HC11 drives

TCLKA and TCLKB of the AD7242/AD7244 while the MOSI

output drives the two serial data lines of the AD7242/AD7244.

The TFSA and TFSB signals are derived from PC6 and PC7,

respectively.

Figure 9. AD7242/AD7244 to TMS320C25 Interface

AD7242/AD7244 to 87C51 Interface

A serial interface between the AD7242/AD7244 and the 87C51

microcontroller is shown in Figure 10. TXD of the 87C51

drives TCLKA and TCLKB of the AD7242/AD7244 while

RXD drives the two serial data lines of the part. The TFSA and

TFSB signals are derived from P3.2 and P3.3, respectively.

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is to be transmitted to the part, PC6 (for DACA) or

PC7 (for DACB) is taken low. When the 68HC11 is configured

like this, data on MOSI is valid on the falling edge of SCK. The

68HCll transmits its serial data in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. To load data

to the AD7242/AD7244, PC6 (for DACA) or PC7 (for DACB)

is left low after the first eight bits are transferred and a second

byte of data is then serially transferred to the AD7242/AD7244.

When the second serial transfer is complete, the PC6 line (for

DACA) or the PC7 line (for DACB) is taken high.

The 87C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. Therefore, the user will have to ensure

that the data in the SBUF register is correctly arranged so the

don’t care bits are the first to be transmitted to the AD7242/

AD7244; the last bit to be sent is the LSB of the word to be

loaded to the AD7242/AD7244. When data is to be transmitted

to the part, P3.2 (for DACA) or P3.3 (for DACB) is taken low.

Data on RXD is valid on the falling edge of TXD. The 87C51

transmits its serial data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. To load data to the

AD7242/AD7244, P3.2 (for DACA) or P3.3 (for DACB) is left

low after the first eight bits are transferred and a second byte of

data is then serially transferred to the AD7242/AD7244. When

the second serial transfer is complete, the P3.2 line (for DACA)

or the P3.3 line (for DACB) is taken high.

Figure 10 shows both LDAC inputs of the AD7242/AD7244

hardwired low. As a result, the DAC latch and the analog

Figure 11. AD7242/AD7244 to 68HC11 Interface

Figure 11 shows both LDAC inputs of the AD7242/AD7244

hardwired low. As a result, the DAC latch and the analog

output of one of the DACs will be updated on the sixteenth

falling edge of SCK after the respective TFS signal for that

DAC has gone low. Alternatively, the scheme used in previous

interfaces, whereby the LDAC inputs are driven from a timer,

can be used.

–10–

REV. A

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