TDA7514
Table 33. SUBADDRESS 18: PLL Test, 456KHz VCO Adjust Start, ISS MP Gain and SD OUT MODE
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
PLL TEST "testdout1" (pin #LFHC)
0
0
0 no test
0
0
1 fref [ref freq divid out]
output, 3V
0
1
0 fsyn [VCO freq div out] output, 3V
0
1
1 phi [VCO prescal out] output, 3V
1
0
0 psm [prescal reset]
output, 3V
1
0
1 phi
input, 3/5V
1
1
0 fsyn
input, 3/5V
1
1
1 sstop (cntres), fsyn
input, 3/5V
PLL TEST "sstop" (pin #SD)
(byte<21>bit<10>=01
0
0
0 no test
0
0
1 ifref
0
1
0 zeroone
output, 3V
output, 3V
output, 3V
0
1
1 stim
1
0
0 ifcout
output, 3V
output, 3V
1
0
1 fsyn
1
1
0 ltst (lock det test)
1
1
1 inlock
output, 3V
output, 3V
output, 3V
456 kHz self-adjustment state machine
0
if byte<19>bit<0>=0 and byte<1>bit<0>=0
0
Waiting
1
0
0
START
Adjacent Channel detector rectifier offset
0.39 V
0
1
1
0
1
1
0
1
0
0.78 V
1.14 V
1.49 V
Quality Seek Mode
fs
Enable seek mode
AdjCh detector filter gain
Filter 2 Gain = 8.5 dB
1
Filter 2 Gain = 14.5 dB
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