SST89E54RD View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST89E54RD Datasheet PDF : 81 Pages
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FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
Data Sheet
Indirect Access:
MOVX@DPTR, A; DPTR contains 0A0H
MOV@R0, #data; R0 contains 90H
Register R0 points to 90H which is located in the upper
address range. Data in “#data” is written to RAM location
90H rather than port 1.
Direct Access:
MOV90H, #data; write data to P1
Data in “#data” is written to port 1. Instructions that write
directly to the address write to the SFRs.
To access the expanded RAM, the EXTRAM bit must be
cleared and MOVX instructions must be used. The extra
768 bytes of memory is physically located on the chip and
logically occupies the first 768 bytes of external memory
(addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly
addressed using the MOVX instruction in combination
with any of the registers R0, R1 of the selected bank or
DPTR. Accessing the expanded RAM does not affect
ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With
EXTRAM = 0, the expanded RAM can be accessed as
in the following example.
Expanded RAM Access (Indirect Addressing only):
DPTR points to 0A0H and data in “A” is written to address
0A0H of the expanded RAM rather than external memory.
Access to external memory higher than 2FFH using the
MOVX instruction will access external memory (0300H to
FFFFH) and will perform in the same way as the standard
8051, with P0 and P2 as data/address bus, and P3.6 and
P3.7 as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will
be similar to the standard 8051. Using MOVX @Ri pro-
vides an 8-bit address with multiplexed data on Port 0.
Other output port pins can be used to output higher order
address bits. This provides external paging capabilities.
Using MOVX @DPTR generates a 16-bit address. This
allows external addressing up the 64K. Port 2 provides the
high-order eight address bits (DPH), and Port 0 multiplexes
the low order eight address bits (DPL) with data. Both
MOVX @Ri and MOVX @DPTR generates the necessary
read and write signals (P3.6 - WR# and P3.7 - RD#) for
external memory use. Table 3-3 shows external data mem-
ory RD#, WR# operation with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the
256 bytes of internal RAM (lower 128 bytes and upper 128
bytes). The stack pointer may not be located in any part of
the expanded RAM.
TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit
MOVX @DPTR, A or MOVX A, @DPTR
AUXR
ADDR < 0300H
ADDR >= 0300H
EXTRAM = 0
EXTRAM = 1
RD# / WR# not asserted
RD# / WR# asserted
RD# / WR# asserted
RD# / WR# asserted
1. Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.
MOVX @Ri, A or MOVX A, @Ri
ADDR = Any
RD# / WR# not asserted1
RD# / WR# asserted
T3-3.0 1255
©2006 Silicon Storage Technology, Inc.
14
S71255-05-000
5/06
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