7. EEPROM data memory
7.1. General description
The EEPROM memory block contains 2048 bytes and is organized in 32 pages (or rows) of 64 bytes. The necessary
high programming voltage is generated on-chip using the standard Vcc pin of the microcontroller.
The EEPROM memory block is located at the addresses 0000h to 07FFh of the XRAM memory space and is
selected by setting control bits in the EECON register.
A read in the EEPROM memory is done with a MOVX instruction.
A physical write in the EEPROM memory is done in two steps : write data in the column latches and transfer of
all data latches in a EEPROM memory row (programming).
The number of data written in the page may vary from 1 to 64 (the page size). When programming, only the data
written in the column latch are programmed. This provides the capability to program the whole memory by bytes,
by page or by a number of bytes in a page.
7.2. Write Data in the column latches
Data is written by byte to the column latches as if it was in an external RAM memory. Out of the 16 address bits
of the data pointer, the 10 MSB are used for page selection and 6 are used for byte selection. Between two
EEPROM programming, all addresses in the column latches must remain in the same page, thus the 10MSB must
The following procedure is used to write in the colums latches :
• Map the program space (Set bit EEE of EECON register)
• Load DPTR with the address to write
• Load A register with the data to be written
• Execute a MOVX @DPTR, A
• If needed loop the three last instructions until the end of a 64bytes page
The EEPROM programming consists on the following actions :
• write one or more bytes in a page in the column latches. Normally, all bytes must belong to the same page;
if this is not the case, the first page address is latched and the others are discarded.
• Set EETIM with the value corresponding to the XTAL frequency.
• Launch the programming by writing the control sequence (52h or 50h followed by A2h or A0h) to the EECON
register (see Table 25).
• EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that EEPROM
segment is not available for read.
• The end of programming is signaled by a hardware clear of the EEBUSY flag.
Rev. F - 15 February, 2001