Table 17. Priority Level Bit Values
Interrupt Level Priority
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 18. IE Register
IE - Interrupt Enable Register (A8h)
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
PCA interrupt enable bit
Clear to disable . Set to enable.
Timer 2 overﬂow interrupt Enable bit
Clear to disable timer 2 overﬂow interrupt.
Set to enable timer 2 overﬂow interrupt.
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overﬂow interrupt Enable bit
Clear to disable timer 1 overﬂow interrupt.
Set to enable timer 1 overﬂow interrupt.
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overﬂow interrupt Enable bit
Clear to disable timer 0 overﬂow interrupt.
Set to enable timer 0 overﬂow interrupt.
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Rev. F - 15 February, 2001