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T89C51RD2-DDFC-L View Datasheet(PDF) - Atmel Corporation

Part Name
Description
Manufacturer
T89C51RD2-DDFC-L
Atmel
Atmel Corporation Atmel
T89C51RD2-DDFC-L Datasheet PDF : 86 Pages
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T89C51RD2
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set
when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module
(Refer to Table 8).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by
hardware when either a match or a capture occurs. These flags also can only be cleared by software.
CCON
Address 0D8H
Symbol
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Table 8. CCON: PCA Counter Control Register
CF
CR
-
CCF4 CCF3 CCF2 CCF1 CCF0
Reset value
0
0
X
0
0
0
0
0
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but
can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
Not implemented, reserved for future use.a
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
The watchdog timer function is implemented in module 4 (See Figure 10).
The PCA interrupt system is shown in Figure 8
Rev. F - 15 February, 2001
24
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